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MAC7200 Datasheet(PDF) 709 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 709 Page - Freescale Semiconductor, Inc

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eSCI Application Usage
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
631
•
Added PMASK Parity Masking
— Added PMSK bit in the SCICR4 register
•
Added unrequested data interrupt
— Added UREQ bit in the LINSTAT2 register
— Added UQIE bit in the LINCTRL3 register
31.8
eSCI Application Usage
Please refer to the eSCI Block Guide for information on using the eSCI in an application.
31.8.1
Enabling the eSCI
Before the eSCI can be used, it must be explicitly enabled by clearing the MDIS bit.
31.9
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
31.9.1
Memory Map
The memory map for the eSCI module is given below. The Address listed for each register is the address
offset. The total address for each register is the sum of the base address for the eSCI module and the
address offset for each register.
Table 31-3. eSCI Memory Map
Offset
Use
Access
0x0
SCI Baud Rate Register High (SCIBDH)
Read/Write
0x1
SCI Baud Rate Register Low (SCIBDL)
Read/Write
0x2
SCI Control Register1 (SCICR1)
Read/Write
0x3
SCI Control Register 2 (SCICR2)
Read/Write
0x4
SCI Control Register 3 (SCICR3)
Read/Write
0x5
SCI Control Register 4 (SCICR4)
Read/Write
0x6
SCI Data Register High (SCIDRH)
Read/Write
0x7
SCI Data Register Low (SCIDRL)
Read/Write
0x8
SCI Status Register 1 (SCISR1)
Read/Write
0x9
SCI Status Register 2 (SCISR2)
Read/Write
0xA
LIN Status Register 1 (LINSTAT1)
Read/Write
0xB
LIN Status Register 2 (LINSTAT2)
Read/Write
0xC
LIN Control Register 1 (LINCTRL1)
Read/Write
0xD
LIN Control Register 2 (LINCTRL2)
Read/Write



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