MAC7200 datasheet(708/976 Pages) FREESCALE

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eSCI Implementation

MAC7200 Microcontroller Family Reference Manual, Rev. 2

630

Freescale Semiconductor

•

Bus Idle Timeout (TTIME_OUT)

25,000 bits

31.4

eSCI Implementation

The eSCI used on the MAC72xx is identical to the eSCI used on the MAC71xx family of devices, except

for the bug fixes and enhancements listed in Section 31.7, “eSCI Differences from MAC71xx.

31.5

eSCI External Pins

31.5.1

SCI Transmit Pin (TXD_A, TXD_B)

These pins serve as transmit data outputs of eSCI_A and eSCI_B.

31.5.2

SCI Receive Pin (RXD)

These pins serve as receive data inputs of eSCI_A and eSCI_B.

31.6

eSCI Bus Aborts

The SCI module supports Peripheral Bus bus aborts, and enforces the following memory map:

Supervisor Access: Unused.

NOTE

Reserved register space inside the “allowed” address range will return $00

for READs, and WRITEs will be ignored.

31.7

eSCI Differences from MAC71xx

•

Added Fast bit error detection in LIN

— Added FBR bit in the SCICR3 register

— Added BESM13 and SBSTP bits in the SCICR4 register

•

Fixed MUCts01378: Fast bit error detection raised RXRDY

•

Fixed MUCts01644: Write on bus abort still writes the register

Table 31-1. eSCI External Pins

TXD_A, TXD_B

Serial Data Transmit

RXD_A, RXD_B

Serial Data Receive

Table 31-2. eSCI Bus Aborts

Abort

Allowed

$0000-$001f

$0020-$3fff

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