MAC7200 datasheet(741/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

663

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge

within the frame. Re-synchronization within frames will correct a misalignment between transmitter bit

times and receiver bit times.

31.10.5.5.1

Slow Data Tolerance

Figure 31-34 shows how much a slow received frame can be misaligned without causing a noise error or

a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data

samples at RT8, RT9, and RT10.

Figure 31-34. Slow Data

In the following discussion RTr represents the receiver RT clock, RTt the transmitter RT clock.

For an 8-bit data character, it takes the receiver

Eqn. 31-4

to start data sampling of the stop bit.

With the misaligned character shown in Figure 31-34, the receiver counts 151 RTr cycles at the point when

the count of the transmitting device is

Eqn. 31-5

The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data

character with no errors is:

Eqn. 31-6

For a 9-bit data character, it takes the receiver

Eqn. 31-7

to start data sampling of the stop bit.

With the misaligned character shown in Figure 31-34, the receiver counts 167 RTr cycles at the point when

the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit

character with no errors is:

Eqn. 31-8

MSB

STOP

DATA

SAMPLES

RECEIVER

RT CLOCK

9 bit times

16 RTr cycles

7 RTr cycles

151 RTr cycles

9 bit times

16 RTt cycles

144 RTt cycles

151

144

–

151

--------------------------

⎝⎠

⎛⎞

100

4.63%

10 bit times

16 RTr cycles

7 RTr cycles

167 RTr cycles

167

160

–

167

--------------------------

⎝⎠

⎛⎞

100

4.19%

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