MAC7200 datasheet(742/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

664

Freescale Semiconductor

31.10.5.5.2

Fast Data Tolerance

Figure 31-35 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10

instead of RT16 but is still sampled at RT8, RT9, and RT10.

Figure 31-35. Fast Data

FoFor an 8-bit data character, it takes the receiver

Eqn. 31-9

to finish data sampling of the stop bit.

With the misaligned character shown in Figure 31-35, the receiver counts 154 RTr cycles at the point when

the count of the transmitting device is

Eqn. 31-10

The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit

character with no errors is:

Eqn. 31-11

For a 9-bit data character, it takes the receiver

Eqn. 31-12

to finish data sampling of the stop bit.

With the misaligned character shown in Figure 31-35, the receiver counts 170 RTr cycles at the point when

the count of the transmitting device is

Eqn. 31-13

The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit

character with no errors is:

Eqn. 31-14

31.10.5.6 Receiver Wakeup

To enable the eSCI to ignore transmissions intended only for other receivers in multiple-receiver systems,

the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register

2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The eSCI will

still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag.

IDLE OR NEXT FRAME

STOP

DATA

SAMPLES

RECEIVER

RT CLOCK

9 bit times

16 RTr cycles

10 RTr cycles

154 RTr cycles

10 bit times

16 RTt cycles

160 RTt cycles

160

154

–

160

--------------------------

⎝⎠

⎛⎞

100

3.75%

10 bit times

16 RTr cycles

10 RTr cycles

170 RTr cycles

11 bit times

16 RTt cycles

176 RTt cycles

176

170

–

176

--------------------------

⎝⎠

⎛⎞

100

3.40%

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