MAC7200 datasheet(847/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

769

Figure 33-18. Flow Diagram for Result Saving/Command Fetching

33.11.5.3 Command / Result Timing

The following figure should illustrate when a conversion result can be expected after a conversion

finished. It also shows at which time the conversion result should be read / transferred at the latest to avoid

the result being overwritten by another conversion:

Figure 33-19. Command vs. Result Timing

Result register

Conversion

a) Result processing

b) New command fetching

Assert DMA

request

Deassert DMA

request

Assert DMA

request

Deassert DMA

request

finished?

Yes

read?

Yes

Command word

ATDCW empty and

current/next conversion not

convert then pause?

Yes

Conv. reset? 1

conversion in progress

result available

Convers. #2

Convers. #3

Convers. #4

Result #1

Result #2

Result #3

Result #4

Idle phase

Convers. #1

No result available

Result should

Idle phase

be read before

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