MAC7200 datasheet(849/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

771

Phase 1: Synchronize external triggers

If chip- external triggers are used to start conversions these triggers must be synchronized to the

system clock which takes two system clock cycles. Refer to Section 33.10.2.2, “ATD External

Trigger Channel Register (ATDETRIGCH),” for details about how to set external triggers.

If chip-internal triggers or no triggers are used then this phase will be skipped.

Phase 2: Conversion startup

Phase two can not be skipped as it is always required. It reflects the conversion startup phase.

Phase 3: Predischarge channel

There is the possibility to predischarge the sample capacitor including the parasitic capacity of an

ATD channel. For further details please See 33.11.7 Conversions Using Predischarge. This phase

is optional and will be skipped if the predischarge feature is not used.

Phase 4: Sample channel

During this phase the sample capacitor is charged with the voltage applied to the channel that

should be converted. This phase can not be skipped. But there is the possibility to set different

sampling lengths.

Phase 5: Convert channel

During this phase the voltage at the sample capacitor is converted and a raw conversion result is

generated. The duration of this phase is independent of the result resolution. This phase can not be

skipped.

Phase 6: Adjust result & conversion shutdown

The raw conversion result can be adjusted to decrease the total unadjusted error (TUE). This

adjustment will take 6 system clock cycles. This phase is optional and will be skipped if the result

adjustment feature is not used.

In parallel and independent to the result adjustment the conversion is shutdown. This will take half

an ATD clock cycle.

The duration of this phase depends on what lasts longer: the result adjustment (if not skipped) or

the conversion shutdown.

Phase 7: Conversion processing

Between phase #1 and phase #6 there are additional system clock cycles needed which have no

mentionable meaning. To keep Figure 33.11.6 simple and to provide the full picture all these clock

cycles have been summed up to phase #7.

Duration of a conversion

The duration of a conversion can easily be calculated by summing up the number of clock cycles

needed for the executed phases.

The following example shows the calculation for one of the longest possible conversions:

1. External triggering selected: 2 SYS

2. Conversion startup: 0.5 ATD

MAC7200 Datasheet(PDF) 849 Page - Freescale Semiconductor, Inc