MAC7200 datasheet(848/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

770

Freescale Semiconductor

33.11.6 Conversion Timing

The following figure should illustrate which phases exist during a conversion. Some of the phases are

predetermined while others provide options:

Figure 33-20. Various Conversion Phases

The boxes contain the number of system clock cycles (x SYS) or ATD clock cycles (x ATD) needed for

the corresponding phase. For details about the relation between the two clocks refer to Section 33.10.2.3,

“ATD Prescaler Register (ATDPRE).”

In case that the number of ATD clocks is specified as “0.5 ATD” the rounded up number of system clock

cycles needed for half an ATD clock is needed. E.g.: If the ATD clock lasts seven times the period of one

system clock (prescaler is seven) then 0.5 ATD clock cycles will last four times the period of one system

clock cycle. If the ATD clock lasts six times the period of one system clock (prescaler is six) then 0.5 ATD

clock cycles will last three times the period of one system clock cycle etc.

The following paragraphs give an overview about the various phases:

Synchronize

Predischarge

2 ATD

8 ATD

64 ATD

128 ATD

Time

1..16 ATD

0.5 ATD

14 ATD

2 SYS

6 SYS

0.5 ATD

5 SYS

Convert channel

Sample channel

Adjust result &

conversion shutdown

Conversion startup

Conversion processing

Always

PRED

ATDTRIGCTL.

TRIGSEL

ATDMODE.

ATDCW.CWSL

ATDCW.CWCH

ATDCW.CWAR

Always

channel(s)

ext. trigger

NOTE: Not drawn to scale

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