MAC7200 datasheet(871/976 Pages) FREESCALE

871 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

793

Interrupt #1 is the only source that has an additional enable bit. Both the CWGI bit in the command word

and the CCIE bit in the ATDINT register must be set in order that the CC flag can generate an interrupt on

the completion of a conversion.

With the ATD module operating in Normal mode, the CC, CP, ETO and CRL flags will be cleared by

writing a ‘1’ to the flag. The CQF, CQE and CQNF flags will not be cleared as these represent the current

state of the command word.

•

Interrupt #1: generated after a conversion finished and CWGI = 1

•

Interrupt #2: generated after a conversion finished and ATDCC[CWCM]= “convert then pause”

•

Interrupt #3: generated when additional edges at the trigger input have been recognized but no

triggers were expected

•

Interrupt #4: generated when a conversion result was overwritten before it could be read

•

Interrupt #5: generated when the command queue is empty

•

Interrupt #6: generated when the command queue is full

•

Interrupt #7: generated when the command queue can store another command word

All interrupts share the same interrupt line. Therefore the flag register must be read to identify the source

of an ATD interrupt.

Table 33-23. ATD Interrupt Vectors

INT#

Interrupt Source

Interrupt

flag

Enable bit

Other

enables

Conversion complete

CCIE

CWGI

Conversion paused

CPIE

—

External trigger overrun

ETO

ETOIE

—

Conversion result lost

CRL

CRLIE

—

Command queue empty

CQE

CQEIE

—

Command queue full

CQF

CQFIE

—

Command queue not full

CQNF

CQNFIE

—

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