MAC7200 datasheet(869/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

791

The following figure shows a similar conversion sequence to that shown in Figure 33-36. Also here Debug

mode is entered during the second conversion. But this time another conversion is started during Debug

mode by writing the ATDCW register:

Figure 33-37. Conversion Procedure for Example 8 (part 2)

After the second conversion finished cmd #3 is not pushed to ATDCC as Debug mode is active. No RX

request for a new command word is asserted as ATDCW is still full. Therefore ATDCC stays empty.

To force the ATD to execute another conversion a new command word must be written to ATDCW. In this

case cmd #3 is written again to ATDCW. This write access will now start a new conversion using cmd #3.

An RX request for a new command word is asserted until a new command word is available (cmd #4).

Once the third conversion finishes ATDCC will run empty. Again it is necessary to write another command

word to ATDCW to start a new conversion. Instead of re-writing cmd #4 to ATDCW this time a new

command (cmd #5) is written to ATDCW. Therefore cmd #4 is overwritten and the ATD will start the

conversion using cmd #5.

After the start ATDCW is empty and therefore another command word is requested. This procedure can

be repeated.

33.12.3.9 Conversion Mechanism (bits CWCH, CWNF, CWGI, CWSC, CWAR)

In Section 33.11.5.2, “Command Processing and DMA Requests,” and Section 33.12.3.4, “Example 4:

Edge-triggered Conversion,” it has been described how conversions are started and what is done after a

conversion finished. This section describes the ATD conversion sequence as well as the remaining bits in

a command word that have not been described previously.

Table 33-22. Bit Description of the Command Word

Bit name

Function

CWCH

Analog channel that must be sampled

CWNF

Numeric format in which the conversion result is saved

CWSL

Sample length (different sample lengths)

CWCM

Conversion mode (see Section 33.11.5.2, “Command Processing and DMA

Requests,” and Section 33.12.3.4, “Example 4: Edge-triggered Conversion”)

CWGI

‘1’ = Set the CC bit in the ATDFLAG register after a conversion finished

empty

cmd #2

cmd #1

empty

RX request

Write ATDCW

ATDCW

ATDCC

ATDRR

empty

Debug-mode

cmd #3

cmd #4

TX request

Read ATDRR

cmd #2

empty

cmd #3

rst #1

rst #2

rst #3

empty

cmd #5

rst #4

empty

cmd #6

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