MAC7200 datasheet(865/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

787

If a trigger arrives after the conversion has been reset this will be flagged as an external trigger overrun

and the ETO flag will be set. In this example there is no additional trigger and therefore the ETO flag

remains unchanged.

Figure 33-30 shows the conversion procedure for this example

Figure 33-30. Conversion Procedure for Example 4

Figure 33-31 illustrates some examples of valid edge-sensitive triggers. The minimum trigger pulse length

must be one system clock cycle. Longer trigger pulses are allowed. The minimum trigger length is

independent of the ATD clock period. Due to synchronization and internal processing, the conversion start

(symbolized by the arrows in Figure 33-31) will be delayed by 4 system clock cycles.

Figure 33-31. ATD Edge-Based Trigger Example

33.12.3.5 Example 5: Level-triggered Conversion

This example shows a conversion started by a high-level sensitive trigger asserted at the analog input

channel 7, as shown in Figure 33-33. The trigger is set up by:

•

ATDTRIGCTL: TRIGSEL = 11 (use analog input channel as trigger)

•

ATDTRIGCTL: TRIGP = 1 (trigger is high-level sensitive)

•

ATDTRIGCTL: TRIGLE = 1 (trigger is level sensitive)

•

ATDETRIGCH: ETRIGCH = 0111 (analog channel #7 is trigger)

empty

cmd #2

cmd #1

empty

cmd #3

rst #1

empty

RX request

Write ATDCW

ATDCW

ATDCC

ATDRR

TX request

Read ATDRR

Conv. complete

cmd #2

rst #2

empty

cmd #3

wait for trig.

convert

Conv. state

idle

Trigger

wait for trig.

convert

wait for trig.

idle

ATD Clock

System

Clock

Minimum

Trigger

Conversion

Start

Valid

Triggers

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