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MAC7200 Datasheet(PDF) 864 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 864 Page - Freescale Semiconductor, Inc

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Initialization/Application Information
MAC7200 Microcontroller Family Reference Manual, Rev. 2
786
Freescale Semiconductor
Figure 33-29. Conversion Procedure for Example 3
After the current conversion was terminated the commands in ATDCC and ATDCW are discarded. As the
the queue is empty again a DMA request for a new command word is asserted. In this example it is
assumed that the whole sequence is repeated which is indicated with cmd #5 and #6. To keep the
togetherness of command and result the third conversion result which belongs to cmd #5 is named rst #5
although it is the third conversion result in this example.
33.12.3.4 Example 4: Edge-triggered Conversion
This example shows how a conversion can be started by a trigger other than a write to the ATDCW. The
example uses a rising-edge sensitive trigger from analog channel #7. The trigger is set up by:
•
ATDTRIGCTL[TRIGSEL] = 11 (use analog input channel as trigger)
•
ATDTRIGCTL[TRIGP] = 1 (trigger is rising-edge sensitive)
•
ATDTRIGCTL[TRIGLE] = 0 (trigger is edge sensitive)
•
ATDETRIGCH[ETRIGCH] = 0_0111 (analog channel #7 is trigger)
Each write to either the ATDTRIGCTL or ATDETRIGCH register will stop any conversion that may be
executing. For this example it is assumed that the registers have been configured previously and no
conversions were being executed.
The following command words are used for this example:
•
CMD #1 .. CMD #3: CWCW = “wait for trigger”
•
CMD #4: CWCM = “conversion reset”
When the first command word is written to the ATDCW register, the CSM will move from state C1 to C2,
where it will wait for a rising edge on the analog input channel 7. When this trigger arrives, the CSM will
transition from state C2 to C3 and the actual conversion will be executed (as described in Section 33.12.3.1,
“Example 1: A Simple Conversion,” to Section 33.12.3.3, “Example 3: Interrupted Conversion
Sequence”).
The second command word is executed in the same way. After this conversion finished and the third
conversion started cmd #4 is written to ATDCW. Immediately after the write the conversion is reset. The
command words in ATDCC and ATDCW are discarded.
empty
cmd #2
cmd #1
cmd #2
cmd #3
empty
empty
#1
empty
cmd #3
empty
rst #1
rst #2
empty
empty
#5 empty
cmd #6
cmd #5
empty
rst #5
cmd #6
RX request
Write ATDCW
ATDCW
ATDCC
ATDRR
TX request
Read ATDRR
#4
empty
Conv. complete



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