MAC7200 datasheet(862/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

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Freescale Semiconductor

3. CMD #4, CMD #5: CWCM= “11” (convert continuously)

After writing the first command (cmd #1) to the ATDCW register the CSM will transition from state C1 to

C3. The command word is pushed from ATDCW to ATDCC.

As ATDCW is again empty the ATD will assert a DMA request to receive a new command word. The state

machine that fetches a new command, now called NSM, will transition from state N1 to N2. It will wait

for a new command word (cmd #2) being written to ATDCW. This process has no influence on the current

conversion. When the command word is available the NSM will go back from state N2 to N1.

After completion of conversion #1 (the result was pushed to ATDRR) the CSM will transition to state C4

where it will check that a new command word is available. As in this example this is the case the CSM

will transition to state C3 which will push the command word from ATDCW to ATDCC and start the

second conversion.

If there was no command word available in ATDCW, the CSM would stay in state C4 until the command

word was received.

In parallel to the second conversion the RSM will assert a DMA request to indicate that there is a result

pending in ATDRR (rst #1).

If the second conversion finishes before the result of the first conversion in the ATDRR register is read a

conversion loss will occur. This will be indicated by setting the CRL flag in the ATDFLAG register. For

this example it is assumed that ATDRR is read in time.

Also during the second conversion the NSM will assert a DMA request to receive a new command word

as ATDCW is empty again. It is assumed that a new command word is available before conversion #2 will

finish.

After completion of conversion #2 the CSM will again transition from C3 to C4 and check the availability

of a new command. As in this example the third command word is available in ATDCW the CSM will

transition to C3 and execute conversion #3.

Again it is assumed that the second conversion result is read before the third conversion finishes.

As the third conversion is “convert then pause” the NSM will not assert a DMA request for a new

command word.

After the third conversion has finished, the CSM will move from state C3 to state C1. This is because the

CWCM bits of the last command word are set to “convert then pause”. The ATD will not start any further

conversions, but will try to save the result of the third conversion.

In Figure 33-28 the conversion procedure like described above is shown:

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