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MAC7200 Datasheet(PDF) 858 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 858 Page - Freescale Semiconductor, Inc |
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858 / 976 page ![]() Initialization/Application Information MAC7200 Microcontroller Family Reference Manual, Rev. 2 780 Freescale Semiconductor To compensate temperature influences it is recommended to do the calibration e.g. every 100 .. 500ms especially when the device is heating up. The calibration frequency might be reduced when the temperature is expected to be stable. 33.12.2.3.1 Sample Special Channel 75% x (VRH -VRL) To sample this channel a command word with the value 0x638B must be written to ATDCW. Table 33-21 shows of what settings this value is composed: When the conversion finished (CC flag is set) the result can be read. To reduce the influence on the conversion result caused by noise on the ATD supply pins this conversion should be repeated several times. Depending on the result variance the mean or median can be used. NOTE When converting this special channel the predischarge feature must be enabled to reduce the influence of parasitic charges. The predischarge time can be two ATD clock cycles or higher. 33.12.2.3.2 Sample Special Channel 25% x (VRH -VRL) To sample this channel a command word with the value 0x638C must be written to ATDCW. This value represents the bit values shown in Table 33-21 but CWCH = 0b0_1100. When the conversion finished (CC flag is set) the result can be read. To reduce the influence on the conversion result caused by noise on the ATD supply pins this conversion should be repeated several times. Depending on the result variance the mean or median can be used. NOTE When converting this special channel the predischarge feature must be enabled to reduce the influence of parasitic charges. The predischarge time can be two ATD clock cycles or higher. Table 33-21. Command Word #1 to Determine Gain and Offset Bit(s) Value Description CWAR 0b0 use raw conversion result CWSC 0b1 special channel CWGI 0b1 Generate an interrupt CWCM 0b00 Continuous conversion CWSL 0b01 Eight ATD clock cycles sampling time CWNF 0b1100 right justified unsigned, 12 bit CWCH 0b0_1011 special channel 75% x (VRH -VRL) |
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