MAC7200 datasheet(861/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

783

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Example 7: Entering Low-power Mode During a Conversion

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Example 8: Debug Mode

Any additional meaning of the remaining command word bits is explained in Section 33.12.3.9,

“Conversion Mechanism (bits CWCH, CWNF, CWGI, CWSC, CWAR)”. If not further specified the

meaning of the bits in ATDCW are either not important for the given example or are intentionally left out

to avoid confusion. All examples refer to the flow diagrams described in Figure 33-17 and Figure 33-18.

33.12.3.1 Example 1: A Simple Conversion

For this example we assume that the ATD has been enabled and tREC has elapsed. At a certain point, a

command word is written to the ATDCW register. It is assumed that CWCM is set to “convert then pause”.

After the write the CSM will immediately go to state C2 and execute the conversion. When the conversion

is finished, the CSM will store the result in the result register ATDRR and then go back to C1

(Figure 33-18). The CSM will also set the pause bit (CP) in the flag register ATDFLAG. If the CPIE bit is

set, an interrupt will be generated.

As there is a result available in ATDRR the Result State Machine (RSM) will transition from R1 to R2

(Figure 33-18b) and will assert a DMA request. The DMA request will stay asserted until the ATDRR

In Figure 33-27 the conversion procedure for this example is shown:

Figure 33-27. Conversion Procedure for Example 1

33.12.3.2 Example 2: A Simple Conversion Sequence (Convert then Pause)

For this example three conversions will be performed in a row with the CSM assumed to be starting from

C1 (Figure 33-17). The command words have the following CWCM bit values:

1. CMD #1, CMD #2: CWCM= “11” (convert continuously)

2. CMD #3: CWCM= “01” (convert then pause)

cmd #1

empty

cmd #1

empty

rst #1

empty

RX request

Write ATDCW

ATDCW

ATDCC

ATDRR

TX request

Read ATDRR

Conv. complete

ATDMODE.MDIS

CSM

RSM

tREC

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