MAC7200 datasheet(870/976 Pages) FREESCALE

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Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

792

Freescale Semiconductor

Each conversion must define which analog channel needs to be sampled. The CWCH bits in the command

word should be programmed with a value from 0 to 31 to identify the appropriate channel number to be

sampled. If the CWSC bit is set then fixed reference voltages can be sampled (see Section 33.10.2.9, “ATD

Command Word Register (ATDCW)”).

When a conversion has been completed, the result is saved using one out of the following numeric formats:

right- justified signed, right-justified unsigned, left-justified signed and left justified unsigned. All of them

are available in four different resolutions (see Section 33.10.2.9, “ATD Command Word Register

(ATDCW)”). The default format is right-justified unsigned 8 bit.

If the CWGI bit is set the Conversion Complete flag (CC) in the ATDCTL register will be set after a

conversion finished. Otherwise the flag will not be updated after the conversion finished. This can be used

to mark the end of a conversion sequence.

E.g. a conversion complete interrupt should be set after 8 conversions were done:

•

CMD #1 .. CMD #7: CWGI = 0

•

CMD #8: CWGI = 1

•

ATDINT.CCIE = 1

The CC flag will remain unchanged after the first seven command words were executed. After the eight

conversions it will get set. If the conversion complete interrupt is enabled an interrupt is generated after

the last conversion finished.

The CWSL bits determine how long the sampling phase should be. It depends on the channel impedance

how long the sampling must last. Usually the minimum value should be enough.

The CWAR bit determines whether the raw conversion result or an adjusted result should be used (See

33.12.2 ATD Calibration / Result Adjustment).

The CWCM bits are already explained in Section 33.11.5.2, “Command Processing and DMA Requests,”

and Section 33.12.3.4, “Example 4: Edge-triggered Conversion.”

33.12.4 Reset

At reset the DMADC1032 is in Disabled mode (see Section 33.11.4, “Low Power / Operating Modes”).

For the reset state of each individual bit see Section 33.10.2, “Register Descriptions.”

33.12.5 Interrupts

The following table provides an overview of the possible ATD interrupt sources. All interrupt flags are

located in the ATDFLAG register, with their enable bits located in the ATDINT register.

CWSC

‘1’ = Sample Special Channels

CWAR

‘1’ = Adjust Result

Table 33-22. Bit Description of the Command Word (Continued)

Bit name

Function

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