MAC7200 datasheet(934/976 Pages) FREESCALE

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Test Controller Introduction

MAC7200 Microcontroller Family Reference Manual, Rev. 2

856

Freescale Semiconductor

Start Flash Lockout Recovery

18:10

(reserved)

n/a

Flash Security Request (Read only)

21:20

n/a

Chip mode (Read only)

Write

Table 35-2. SC4 Test Register Field Descriptions

Field

Description

Core is running

When this bit is set, the core is running. When it is cleared, the core is suspended by negating the CLKEN input of

the ARM7 core. This bit may be written or read in any mode, with TEST = 0 or 1. It is used primarily in MBIST or

NVMBIST modes to prevent any possible interaction between the core and the BIST engines.

1–4

Device ID (Read only)

These four bits contain the last four digits of the device ID.

Reset debug logic

When this bit is set, it causes the system debug reset to be asserted. This resets the following logic:

• EICE (DBGnTRST input on the ARM7 core)

• Test Registers SC4, SC5, SC6 and SC7 and associated logic

• JTAG synchronization logic

Since setting this bit in JTAG register SC4 causes JTAG Register SC4 itself to be cleared, you must not perform any

other operations during this write. This bit may be written while RESET is asserted, but the value will not take effect

until after RESET has been negated.

Resetting of the Nexus registers is not done via this bit. In order to reset the Nexus registers, you must perform either

a Power On Reset (POR) or cycle the ARM7 TAP State Machine through the Test Reset state.

6–7

(reserved)

Flash Lockout Recovery is complete (Read only)

This read-only bit will be set once the JTAG Lockout Recovery sequence has completed. It does not indicate whether

the sequence was successful (this is indicated by bit 19), but is used to determine when the sequence has completed

and the status of the chip security may be read out.

After the JTAG Lockout Recovery has completed a reset must be issued to reload the security of the device from the

shadow.

Start Flash Lockout Recovery

Setting this bit will start the JTAG Lockout Recovery sequence. Note that it is necessary to manually clear this bit

once the sequence has started or completed.

10–18

(reserved)

Flash Security Request (Read only)

20–21

Chip mode (Read only)

Write

Table 35-1. SC4 Test Register Field Definitions (Continued)

Field

Reset

Value

Function

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