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MAC7200 Datasheet(PDF) 963 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 963 Page - Freescale Semiconductor, Inc |
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963 / 976 page ![]() Analog-to-Digital Converter Characteristics MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 885 A.16.1 Factors Influencing Accuracy The main factors influencing the ATD accuracy are the supply voltages (VRL, VRH, VSSA and VDDA) and the ATD conversion clock frequency fATDCLK. Please see Table A-31 for details. A.16.2 ATD Accuracy Table A-31 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. V6 C Analog Reference Supply Current (VRH, VRL) IREF —— 1 mA V7 C Disruptive Input Injection Current2 3 4 INA –1.0 — 1.0 mA 1. All voltages referred to VSSA, –40 to 125 oC, V DDA = 5.0 V ±10% and 2.0 MHz conversion rate unless otherwise noted. Refer to Table A-5 for additional operating conditions. 2. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VRH <= VDDA and VRL >= VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 3. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 4. Condition applies to two adjacent pins. Table A-30. ATD Electrical Characteristics Conditions are shown in Table A-5 unless otherwise noted Num C Rating Symbol Min Typ Max Unit W1 T Total Input Capacitance (Non Sampling) CINN —— 10 pF W2 Stop Mode Recovery Time1 1. Stop mode recovery time is the time from the setting of either of the enable bits in the ATD Control Register to the time that the ATD is ready to perform conversions. TREC —— 10 μs Table A-31. ATD Conversion Performance in 5 V Range Conditions shown in Table A-5 unless otherwise noted. VREF = VRH – VRL = 5.12 V, resulting in one 9 bit count = 10 mV and one 12 bit count = 1.25 mV fATDCLK = 12 MHz, VDDA -0.1V ≤ VRH ≤ VDDA + 0.1V, with calibration, a source impedance of < 150 ohm, no precondition, WARP on. Num C Rating Symbol Min Typ Max Unit X1 P Resolution1 LSB 1.25 — — mV X2 P Differential Nonlinearity @12MHz ATD clock and 12-bit resolution DNL -8 — +8 Counts Table A-29. ATD Electrical Characteristics (Operating)1 (Continued) Num C Rating Symbol Min Typ Max Unit |
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