MAC7200 datasheet(964/976 Pages) FREESCALE

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Analog-to-Digital Converter Characteristics

MAC7200 Microcontroller Family Reference Manual, Rev. 2

886

Freescale Semiconductor

For the following definitions see also Figure A-13.

DNL — Differential Non Linearity Error

The measured device output codes are normalized, and the difference of each code width from 1 LSB is

measured. The largest difference is reported as the DNL.

Eqn. A-14

where

•

x = location in the normalized results array where a voltage ramp begins

•

y = location in the normalized results array where a voltage ramp ends

•

ViStart = the input voltage when the observed normalized output changes

•

ViEnd = the input voltage when the normalized output changed previously

•

Bitweight = volts per LSB step

INL — Integral (Cumulative) Non Linearity Error

The measured output codes are normalized and compared against the codes that would be produced by an

ideal ATD. The difference is taken between each measured transition point and the corresponding

transition point for the ideal ATD. The largest difference is reported as INL.

Eqn. A-15

P Integral Nonlinearity @12MHz ATD clock and

12-bit resolution

INL

-8

—

Counts

P Total unadjusted Error2 @12MHz ATD clock and

12-bit resolution3:

VRL + 100mV <= Vin <= VRH - 100mV

TUE

-8

—

Counts

0 <= Vin < VRL + 100mV

and

VRH -100mV <= Vin <VRH

-16

—

+16

C Source Impedance4

RSource

—

100

kohm

1. At VRH - VRL = 5.12V, one LSB = 1.25mV = one count

2. These values include the quantization error which is inherently 1/2 count for any A/D converter.

3. The TUE specification will always be better than the sum of the INL and DNL errors due to cancelling errors.

4. If using a source impedance greater than 150 ohm, then the customer should characterize the ATD sample clock

value.

Table A-31. ATD Conversion Performance in 5 V Range (Continued)

Conditions shown in Table A-5 unless otherwise noted.

VREF = VRH – VRL = 5.12 V, resulting in one 9 bit count = 10 mV and one 12 bit count = 1.25 mV

fATDCLK = 12 MHz, VDDA -0.1V ≤ VRH ≤ VDDA + 0.1V, with calibration, a source impedance of < 150 ohm, no

precondition, WARP on.

i = x

MAX[ABS(ViStart - ViEnd) - Bitweight]

i = x

MAX[(ViActual - ViIdeal)]

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