TLC5949PWPR datasheet(33/51 Pages) TI

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TLC5949

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SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

Table 12. PSM Select Truth Table: Bits 135, 134

PSMODE

BIT 135

BIT 134

POWER-SAVE MODE (PSM) FUNCTION

Power-save mode is disabled in every condition

When all '0's are written into the second GS data latch, the device goes into

power-save mode. When an SCLK rising edge occurs, the device goes to normal

operation and starts to control the output current. However, some recovery time

(tD7) is required to resume normal operation after an SCLK rising edge.

When all '0's are written into the second GS data latch, the device goes into

power-save mode. When the data (except all '0's) are written into the second GS

data latch, the device goes to normal operation and starts to control the output

current. However, some recovery time (tD7) is required to resume normal operation

after the data changes.

Power-save mode is enabled in every condition. When the device is powered up,

1 (default)

this mode is selected.

Table 13. PSM Select Truth Table: Bit 136

PSMODE

BIT 136

POWER-SAVE MODE (PSM) FUNCTION

The GSCLK signal is used for GS timing control in the same manner as in normal mode even if the

device is in power-save mode.

When the device is in power-save mode, the GSCLK signal is forced low internally and GS timing

control logic is not operational in order to reduce power consumption. However, if the lower two bits of

1 (default)

PSMODE (bits 135, 134) are set to '0', the GSCLK signal is not forced low because the PSM is

disabled. When the device is powered up, this mode is selected.

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