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TLC5949PWPR Datasheet(PDF) 27 Page - Texas Instruments |
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TLC5949PWPR Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 51 page  Lower 137 Bits of 192 Bits SOUT SCLK SIN Common Shift Register (193Bits) MSB Lower 192 Bits 1 2 3 4 5 187 188 189 190 191 192 Latch Select Bit Common Data Bit 191 Common Data Bit 190 Common Data Bit 189 Common Data Bit 188 Common Data Bit 187 Common Data Bit 5 Common Data Bit 4 Common Data Bit 3 Common Data Bit 2 Common Data Bit 1 This latch pulse comes from the LAT pin when the MSB of the Common Shift Register is ‘1’. LSB 0 Common Data Bit 0 192 Bits First Grayscale (GS) Data Latch (192 Bits) MSB 191 48 180 GS Data for OUT15 OUT15 Bit 15 OUT15 Bit 0 OUT3 Bit 0 32 47 OUT2 Bit 15 OUT2 Bit 0 GS Data for OUT2 16 31 OUT1 Bit 15 OUT1 Bit 0 GS Data for OUT1 LSB 0 15 OUT0 Bit 15 OUT0 Bit 0 GS Data for OUT0 This latch pulse comes from the LAT pin when the MSB of the Common Shift Register is '0'. 192 Bits Second Grayscale (GS) Data Latch (192 Bits) MSB 191 48 180 GS Data for OUT15 OUT15 Bit 15 OUT15 Bit 0 OUT3 Bit 0 32 47 OUT2 Bit 15 OUT2 Bit 0 GS Data for OUT2 16 31 OUT1 Bit 15 OUT1 Bit 0 GS Data for OUT1 LSB 0 15 OUT0 Bit 15 OUT0 Bit 0 GS Data for OUT0 The 4096th GSCLK is used to latch the data when the Auto Display Repeat is enabled or when the BLANK bit is set to '1'. 192 Bits To GS Timing Control Circuit Second Control Data Latch (119 Bits) 7 Bits 112 Bits 13-7 20-14 27-21 97-91 104-98 111-105 MSB 118-112 90-84 BC Bits[6:0] for OUTn To Global Brightness Control Circuit No Applied Bits LSB 6-0 The 4096th GSCLK is used to latch the data when the Auto Display Repeat is enabled or when the BLANK bit is set to '1'. RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits BC, 7 Bits 112 Reserved Bits (Write '1' to All Bits) First Control Data Latch (137 Bits) 18 Bits MSB 136-119 13-7 20-14 27-21 97-91 104-98 111-105 118-112 FC, 18 Bits 90-84 FUNC Bits 17-0 BC Bits[6:0] for OUTn To Function Control Circuit LSB 6-0 RSV Bits (1) RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits RSV Bits BC, 7 Bits 112 Bits (Write ‘1’ to All Bits) Reserved 119 Bits TLC5949 www.ti.com SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012 REGISTER AND DATA LATCH CONFIGURATION The TLC5949 has one common shift register and two pairs of data latches: the first and second grayscale (GS) data latches and the first and second control data latches. The common shift register is 193 bits long and the GS data latches are 192 bits long in total. The first control data latch is 137 bits long and the second latch is 119 bits long. When the common shift register MSB is '0', the least significant 256 bits from the common shift register are latched into the first GS data latch. When the MSB is '1', the data are latched into the first control data latch. Figure 27 shows the common shift register and latch configurations. (1) RSV = reserved. Figure 27. Common Shift Register and Control Data Latches Configuration Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: TLC5949 |
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