4096

4094

4095

1

2

3

32nd

Period

17th

Period

24th

Period

3967

3970

3968

3969

127

129

128

130

GSCLK

BLANK Bit in the

First Control Data Latch

(Internal)

(1)

ON

OFF

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

1022

1025

1023

1026

1024

1027

3070

3073

3071

3074

3072

3075

1st Period

25th

Period

31st

Period

(Voltage Level = High)

Note (2)

2nd

Period

8th

Period

16th

Period

9th

Period

2046

2049

2047

2050

2048

2051

1st

Period

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

t = GSCLK

128

´

OFF

OUTn

(GS Data = 000h)

OUTn

(GS Data = 001h)

OUTn

(GS Data = 002h)

OUTn

(GS Data = 003h)

OUTn

(GS Data = 004h)

OUTn

(GS Data = 010h)

OUTn

(GS Data = 020h)

OUTn

(GS Data = 021h)

OUTn

(GS Data = 022h)

OUTn

(GS Data = F80h)

OUTn

(GS Data = F81h)

OUTn

(GS Data = FFEh)

OUTn

(GS Data = FFFh)

t =

GSCLK

127

´

t =

GSCLK

127

´

t = GSCLK

128

´

t = GSCLK

128

´

ON

¼

¼

¼

¼

¼

¼

¼

¼

¼

¼

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

(Voltage Level = Low)

t = GSCLK

1d

´

t =

GSCLK

127

´

t = GSCLK

127 in 2nd to 32nd Period

´

t = GSCLK

127 in 2nd to

Period

´

32nd

t = GSCLK

128 in 2nd to 31st Period

´

t = GSCLK

128 in 2nd to 15th and 17th to

Periods,

t = GSCLK

127 in 16th Period

´

´

31st

t = GSCLK

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

2d

´

t = GSCLK

2d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

2d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

t = GSCLK

1d

´

TLC5949

www.ti.com

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

(1) The internal signal is generated when LAT inputs GS data when the display timing reset bit (TMGRST) is set to '1'. This signal has the

same function as BLANK = 1. Furthermore, the signal is generated at the 4096th GSCLK when the auto display repeat bit (DSPRPT) is set to

'1'.

(2) When auto display repeat is on.

Figure 23. ES PWM Operation

Copyright © 2012, Texas Instruments Incorporated

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