TLC5949PWPR datasheet(38/51 Pages) TI

38 / 51 page

2 A, 10 A, 20

mA,

or 1 mA

OUT Current for IDM

'0'

193-Bit Common Shift

(Internal)

SID Loaded Into Common Shift Register

GS Data

LAT

'1'

LOD

XXXh

LOD

XXXh

LOD

000h

LOD

XXXh

LOD data are not stable immediately after OUT turn on.

LOD and LSD Data Latch

(Internal)

16-Bit LOD and LSD

Circuit Output Data

(Internal)

LOD and LSD Old Data

LOD

XXXh

0 A

LOD, LSD

000h

LOD

XXXh

0 A

2 A, 10 A, 20

LOD and LSD data latch updated with latest

data at the clock time selected by LATTMG bit.

OUT Current

for PWM Control

(GSDATA = FFFh)

0 mA

(2)

Programmed

Output Current

BLANK Bit

in Control Data Latch

(Internal)

2 3

16 17 18 19 20

4093

4095

4094

4096

LOD

XXXh

Control Data

Unknown

'1'

TMGRST Bit

in Control Data Latch

(Internal)

(1)

Internal BLANK is generated when the LAT

signal is input because display timing reset is enabled.

Control data write

latch signal.

GS data write latch signal.

(3)

TLC5949

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

www.ti.com

(1) Set the current with the external resistor and BC data.

(2) Select the output current with the IDMCUR bit in the control data latch.

(3) Select clock time with the LATTMG bit in the control data latch.

Figure 32. PWM Operation Timing

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TLC5949PWPR Datasheet(PDF) 38 Page - Texas Instruments

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