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TLC5949PWPR Datasheet(PDF) 26 Page - Texas Instruments

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Part # TLC5949PWPR
Description  16-Channel, 12-Bit, ES-PWM, Full Self-Diagnosis LED Driver for 7-Bit Global BC LED Lamp
PDF  51 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TLC5949PWPR Datasheet(HTML) 26 Page - Texas Instruments

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'0'
Control Data Write
RSV
0A
Not
Valid
GS0
1A
SCLK
First GS Data Latch
(Internal)
GSCLK
Second GS Data Latch
(Internal)
OUTn
Common Shift Register
(Internal)
LAT
OFF
ON
GS0
4A
GS0
3A
GS0
2A
GS0
0A
High
RSV
0A
(1)
Not
Valid
New GS Data
Old GS Data
Old GS Data
New GS Data
New Data
Old Control Data
Old Control Data
GS and BC Controlled by Old Data
Note (3)
BLANK Bit
in First Control Data Latch
(Internal)
(2)
Data = 0
First Control Data Latch
(Internal)
Second Control Data Latch
(Internal)
SIN
SOUT
Low
(Bit 193 Data)
GS15
15A
GS Data Write
Control Data Write
Not
Valid
RSV
1A
RSV
2A
RSV
3A
GS15
14A
GS15
13A
GS0
0A
GS0
1A
GS0
2A
High
(Bit 193 Data)
188
189
190
191
192
193
1
2
3
190
191
192
193
1
2
3
193
Not
Valid
High
Not
Valid
1
2
3
New Data
High
Data = 1
New Data
TLC5949
SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012
www.ti.com
(1) RSV = reserved.
(2) The BLANK bit value is changed after the LAT rising edge.
(3) GS and BC are controlled by new data.
Figure 26. Auto Data Refresh Function 2
Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge for a GS data write.
This function can be switched on or off with the TMGRST bit in the first control data latch. When the TMGRST bit
is '1', the GS counter is reset to '0' and all outputs are forced off at the LAT rising edge for a GS data write.
Furthermore, the data in the 193-bit common shift register are copied to the first and second GS data latches at
the same time. In addition, the BC data in the first control data latch are transferred to the second data latch
simultaneously. This configuration is identical to the BLANK bit when it changes data from '0' to '1' and '1' to '0'.
Therefore, the BLANK bit is not required to control the display reset. PWM control resumes from the next GSCLK
rising edge. When the TMGRST bit is '0', the GS counter is not reset and the outputs are not forced off even with
a LAT rising edge.
26
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC5949



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