1

2

3

4

No drivers turn on when GS data are '0'.

GSCLK

OUTn

(GSDATA = 000h)

ON

OFF

ON

OFF

t = GSCLK

1

´

OUTn

(GSDATA = 001h)

ON

OFF

t = GSCLK

2

´

ON

OFF

t = GSCLK

3

´

ON

OFF

ON

OFF

OUTn

(GSDATA = 002h)

OUTn

(GSDATA = 003h)

OUTn

(GSDATA = 7FFh)

OUTn

(GSDATA = 800h)

ON

OFF

ON

OFF

ON

OFF

OUTn

(GSDATA = FFEh)

OUTn

(GSDATA = FFFh)

OUTn

(GSDATA = 801h)

ON

OFF

OUTn

(GSDATA = FFDh)

See (2)

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

2048

2049

2050

BLANK Bit

(Internal)

(1)

1

2

3 4

4095

4096

4097

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

(V

)

OUTnH

(V

)

OUTnL

See (3)

See (4)

t = GSCLK

2048

´

t = GSCLK

4095

´

t = GSCLK

2049

´

t = GSCLK

4093

´

t = GSCLK

4094

´

t = GSCLK

2047

´

TLC5949

www.ti.com

SBVS219A – DECEMBER 2012 – REVISED DECEMBER 2012

(1) The internal signal is generated when LAT inputs GS data with the display timing reset bit (TMGRST) set to '1'. This signal has the same

function as a BLANK = 1 pulse. Furthermore, the signal is generated at the 4096th GSCLK when the auto display repeat bit (DSPRPT) is set

to '1'.

(2) The GS counter begins to count GSCLK pulses after the BLANK bit is set to '0' or when the LAT signal for a GS data write is input with

the display time reset mode enabled.

(3) OUTn turns on at the first GSCLK rising edge except when GS data are '0' after the BLANK bit is set to '0' or when the LAT signal for a

GS data write is input with the display time reset mode enabled.

(4) OUTn does not turn on again until BLANK is set to '1' at least one time, except when the TMGRST or DSPRPT bits are '1'.

Figure 22. Conventional PWM Operation

Copyright © 2012, Texas Instruments Incorporated

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