ASD1194 datasheet(41/76 Pages) TI

41 / 76 page

ADS1194, ADS1196

ADS1198

www.ti.com

SBAS471C

– APRIL 2010 – REVISED NOVEMBER 2011

CONFIG1: Configuration Register 1

Address = 01h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DAISY_EN

CLK_EN

DR2

DR1

DR0

Bit 7

Must always be set to '0'

Bit 6

DAISY_EN: Daisy-chain/multiple readback mode

This bit determines which mode is enabled.

0 = Daisy-chain mode (default)

1 = Multiple readback mode

Bit 5

CLK_EN: CLK connection(1)

This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin = 1.

0 = Oscillator clock output disabled (default)

1 = Oscillator clock output enabled

Bits[4:3]

Must always be set to '0'

Bits[2:0]

DR[2:0]: Output data rate.

fMOD = fCLK/16.

These bits determine the output data rate of the device.

(1)

Additional power will be consumed when driving external devices.

BIT

DATA RATE

SAMPLE RATE(1)

000

fMOD/16

8kSPS

001

fMOD/32

4kSPS

010

fMOD/64

2kSPS

011

fMOD/128

1kSPS

100 (default)

fMOD/256

500SPS

101

fMOD/512

250SPS

110

fMOD/1024

125SPS

111

DO NOT USE

N/A

(1)

fCLK = 2.048MHz.

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Product Folder Link(s): ADS1194 ADS1196 ADS1198

ASD1194 Datasheet(PDF) 41 Page - Texas Instruments

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