ASD1194 datasheet(45/76 Pages) TI

45 / 76 page

ADS1194, ADS1196

ADS1198

www.ti.com

SBAS471C

– APRIL 2010 – REVISED NOVEMBER 2011

CHnSET: Individual Channel Settings (n = 1:8)

Address = 05h to 0Ch

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

GAIN2

GAIN1

GAIN0

MUXn2

MUXn1

MUXn0

The CH[1:8]SET Control Register configures the power mode, PGA gain, and multiplexer settings channels. See

the Input Multiplexer section for details. CH[2:8]SET are similar to CH1SET, corresponding to the respective

channels.

Bit 7

PD: Power-down

This bit determines the channel power mode for the corresponding channel.

0 = Normal operation (default)

1 = Channel power-down. When powering down a channel, it is recommended that the channel be set to input short by

setting the appropriate MUXn[2:0] = 001 of the CHnSET register.

Bits[6:4]

GAIN[2:0]: PGA gain

These bits determine the PGA gain setting.

000 = 6 (default)

001 = 1

010 = 2

011 = 3

100 = 4

101 = 8

110 = 12

Bit 3

Always write '0'

Bits[2:0]

MUXn[2:0]: Channel input

These bits determine the channel input selection.

000 = Normal electrode input (default)

001 = Input shorted (for offset or noise measurements)

010 = Used in conjunction with RLD_MEAS bit for RLD measurements. See the Right Leg Drive (RLD DC Bias Circuit)

subsection of the ECG-Specific Functions section for more details.

011 = MVDD for supply measurement

100 = Temperature sensor

101 = Test signal

110 = RLD_DRP (positive electrode is the driver)

111 = RLD_DRN (negative electrode is the driver)

RLD_SENSP

Address = 0Dh

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RLD8P

RLD7P

RLD6P

RLD5P

RLD4P

RLD3P

RLD2P

RLD1P

This register controls the selection of the positive signals from each channel for right leg drive derivation. See the

Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.

Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194/6.

RLD_SENSN

Address = 0Eh

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RLD8N

RLD7N

RLD6N

RLD5N

RLD4N

RLD3N

RLD2N

RLD1N

This register controls the selection of the negative signals from each channel for right leg drive derivation. See

the Right Leg Drive (RLD DC Bias Circuit) subsection of the ECG-Specific Functions section for details.

Note that registers bits[5:4] are not available for the ADS1194. Bits[7:6] are not available for the ADS1194 and

ADS1196.

Submit Documentation Feedback

Product Folder Link(s): ADS1194 ADS1196 ADS1198

ASD1194 Datasheet(PDF) 45 Page - Texas Instruments

ASD1194 Datasheet(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL