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ASD1194 Datasheet(PDF) 12 Page - Texas Instruments

Part # ASD1194
Description  Low-Power, 8-Channel, 16-Bit Analog Front-End for Biopotential Measurements
PDF  76 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ASD1194 Datasheet(HTML) 12 Page - Texas Instruments

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background image
1
CS
SCLK
DIN
DOUT
2
3
8
1
2
8
3
t
CSSC
t
DIST
t
DIHD
t
DOHD
t
CSH
t
DOPD
t
SPWH
t
SPWL
t
SCCS
Hi-Z
t
CSDOZ
t
CSDOD
Hi-Z
t
SCLK
t
SDECODE
CLK
t
CLK
D ISY_IN
A
DOUT
SCLK
MSB
D1
t
DISCK2ST
MSB
2
1
3
152
153
154
MSB
D1
LSB
t
DISCK2HT
t
DOPD
Don’tCare
LSB
D1
155
ADS1194, ADS1196
ADS1198
SBAS471C
– APRIL 2010 – REVISED NOVEMBER 2011
www.ti.com
TIMING CHARACTERISTICS
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
NOTE: Daisy-chain timing is shown for the 8-channel ADS1198.
Figure 2. Daisy-Chain Interface Timing
Timing Requirements For Figure 1 and Figure 2
Specifications apply from 0
°C to +70°C. Load on DOUT = 20pF || 100kΩ.
2.7V
≤ DVDD ≤ 3.6V
1.65V
≤ DVDD ≤ 2.0V
PARAMETER
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
tCLK
Master clock period
414
514
414
514
ns
tCSSC
CS low to first SCLK; setup time
6
17
ns
tSCLK
SCLK period
50
66.6
ns
tSPWH, L
SCLK pulse width, high and low
15
25
ns
tDIST
DIN valid to SCLK falling edge; setup time
10
10
ns
tDIHD
Valid DIN after SCLK falling edge; hold time
10
11
ns
tDOHD
SCLK falling edge to invalid DOUT; hold time
10
10
ns
tDOPD
SCLK rising edge to DOUT valid; setup time
17
32
ns
tCSH
CS high pulse
2
2
tCLKs
tCSDOD
CS low to DOUT driven
8
20
ns
tSCCS
Eighth SCLK falling edge to CS high
4
4
tCLKs
tSDECODE
Command decode time
4
4
tCLKs
tCSDOZ
CS high to DOUT Hi-Z
10
20
ns
tDISCK2ST
DAISY_IN valid to SCLK rising edge; setup time
10
10
ns
tDISCK2HT
DAISY_IN valid after SCLK rising edge; hold time
10
10
ns
12
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Copyright
© 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS1194 ADS1196 ADS1198



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