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ASD1194 Datasheet(PDF) 32 Page - Texas Instruments |
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ASD1194 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 76 page  START 1 ADS1198 1 CLK DRDY DRDY 1 START CLK START 2 ADS1198 2 CLK DRDY DRDY 2 START CLK DRDY 1 DRDY 2 t SETTLE ADS1194, ADS1196 ADS1198 SBAS471C – APRIL 2010 – REVISED NOVEMBER 2011 www.ti.com When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on the settling times). Figure 35 shows the behavior of two devices when synchronized with the START signal. There are two ways to connect multiple devices with a optimal number of interface pins: cascade mode and daisy-chain mode. Figure 35. Synchronizing Multiple Converters 32 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS1194 ADS1196 ADS1198 |
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