ASD1194 datasheet(26/76 Pages) TI

26 / 76 page

ADS1194, ADS1196

ADS1198

SBAS471C

– APRIL 2010 – REVISED NOVEMBER 2011

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SPI INTERFACE

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads

conversion data, reads and writes registers, and controls the ADS1194/6/8 operation. The DRDY output is used

as a status signal to indicate when data are ready. DRDY goes low when new data are available.

Chip Select (CS)

Chip select (CS) selects the ADS1194/6/8 for SPI communication. CS must remain low for the entire duration of

the serial communication. After the serial communication is finished, always wait eight or more tCLK cycles before

taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT

enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is

high or low.

Serial Clock (SCLK)

SCLK is the serial peripheral interface (SPI) serial clock. It is used to shift in commands and shift out data from

the device. The serial clock (SCLK) features a Schmitt-triggered input and clocks data on the DIN and DOUT

pins into and out of the ADS1194/6/8. Even though the input has hysteresis, it is recommended to keep SCLK as

clean as possible to prevent glitches from accidentally shifting the data. The absolute maximum limit for SCLK is

specified in the Serial Interface Timing table. When shifting in commands with SCLK, make sure that the entire

set of SCLKs is issued to the device. Failure to do so results in the device being placed into an unknown state,

requiring CS to be taken high to recover.

For a single device, the minimum speed needed for the SCLK depends on the number of channels, number of

bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the

Multiple Device Configuration section.)

tSCLK < (tDR – 4tCLK)/(NBITS × NCHANNELS + 24)

For example, if the ADS1198 is used in a 500SPS mode (8 channels, 16-bit resolution), the minimum SCLK

speed is 80kHz.

Data retrieval can be done either by putting the device in RDATAC mode or by issuing a RDATA command for

data on demand. The above SCLK rate limitation applies to RDATAC. For the RDATA command, the limitation

applies if data must be read in between two consecutive DRDY signals. The above calculation assumes that

there are no other commands issued in between data captures.

Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data to the ADS1194/6/8 (opcode commands and

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ASD1194 Datasheet(PDF) 26 Page - Texas Instruments