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LPC4370 Datasheet(PDF) 125 Page - NXP Semiconductors

Part # LPC4370
Description  32-bit ARM Cortex-M4 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals
PDF  150 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4370 Datasheet(HTML) 125 Page - NXP Semiconductors

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LPC4370
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 October 2013
125 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
[1]
The ADC is monotonic, there are no missing codes.
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 37.
[3]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 37.
[4]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 37.
[5]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 37.
[6]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 37.
[7]
Tamb = 25 C; maximum sampling frequency fs = 4.5 MHz and analog input capacitance Cia = 2 pF.
[8]
Input resistance Ri depends on the sampling frequency fs: Ri = 2 k + 1 / (fs  Cia).
Table 35.
10-bit ADC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; ADC frequency 4.5 MHz; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDDA(3V3)
V
Cia
analog input
capacitance
--
2
pF
ED
differential linearity error
[1][2] -
0.8
-
LSB
-
1.0
-
LSB
EL(adj)
integral non-linearity
[3] -
0.8
-
LSB
-
1.5
-
LSB
EO
offset error
[4] -
0.15
-
LSB
-
0.15
-
LSB
EG
gain error
[5] -
0.3
-
%
-
0.35
-
%
ET
absolute error
[6] -
3-
LSB
-
4-
LSB
Rvsi
voltage source interface
resistance
see Figure 38
--
1/(7
 f
clk(ADC)
 C
ia)
k
Ri
input resistance
[7][8] --
1.2
M
fclk(ADC)
ADC clock frequency
-
-
4.5
MHz
fc(ADC)
ADC conversion
frequency
10-bit resolution; 11 clock
cycles
-
-
400
kSamples/s
2-bit resolution; 3 clock
cycles
1.5
MSamples/s



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