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A40MX02 Datasheet(PDF) 32 Page - Microsemi Corporation |
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A40MX02 Datasheet(HTML) 32 Page - Microsemi Corporation |
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32 / 142 page  40MX and 42MX FPGA Families 1- 28 R e v i sio n 1 1 Notes: 1. Load-dependent 2. Values are shown for A42MX36 –3 at 5.0 V worst-case commercial conditions. Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks) t SUD = 3.0 ns t HD = 0.0 ns FMAX=180 MHz t CKH=3.03 ns 1 Quadrant Clocks t CO = 1.3 ns t RD1 = 0.9 ns Sequential Logic Module t LH = 0.00 ns t LSU = 0.5 ns t GHL = 2.9 ns t ENHZ = 5.3 ns t DLH = 2.6 ns t RDD = 0.3 ns t PDD = 1.6 ns t INH = 0.0 ns t INSU = 0.5 ns t INGO = 1.4 ns t RD1 = 0.9 ns t RD2 = 1.3 ns t RD4 = 2.0 ns t DLH = 2.6 ns t PD=1.3 ns t INPY = 1.0 ns t IRD1= 2.0 ns I/O Module Combinatorial Module I/O Module Decode Module Comb. Logic Include D Q DQ G G D Q I/O Module Input Delays Internal Delays Output Delays Predicted Routing Delays |
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