A40MX02 datasheet(44/142 Pages) MICROSEMI

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40MX and 42MX FPGA Families

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Timing Characteristics

Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Units

Parameter / Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Logic Module Propagation Delays

tPD1

Single Module

1.2

1.4

1.6

1.9

2.7

tPD2

Dual-Module Macros

2.7

3.1

3.5

4.1

5.7

tCO

Sequential Clock-to-Q

1.2

1.4

1.6

1.9

2.7

tGO

Latch G-to-Q

1.2

1.4

1.6

1.9

2.7

tRS

Flip-Flop (Latch) Reset-to-Q

1.2

1.4

1.6

1.9

2.7

Logic Module Predicted Routing Delays1

tRD1

FO = 1 Routing Delay

1.3

1.5

1.7

2.0

2.8

tRD2

FO = 2 Routing Delay

1.8

2.1

2.4

2.8

3.9

tRD3

FO = 3 Routing Delay

2.3

2.7

3.0

3.6

5.0

tRD4

FO = 4 Routing Delay

2.9

3.3

3.7

4.4

6.1

tRD8

FO = 8 Routing Delay

4.9

5.7

6.5

7.6

10.6

Logic Module Sequential Timing2

tSUD

Flip-Flop (Latch)

Data Input Set-Up

3.1

3.5

4.0

4.7

6.6

tHD

Flip-Flop (Latch)

Data Input Hold

0.0

tSUENA Flip-Flop (Latch)

Enable Set-Up

3.1

3.5

4.0

4.7

6.6

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA Flip-Flop (Latch)

Clock Active Pulse Width

3.3

3.8

4.3

5.0

7.0

tWASYN Flip-Flop (Latch)

Asynchronous Pulse Width

3.3

3.8

4.3

5.0

7.0

Flip-Flop Clock Input Period

4.8

5.6

6.3

7.5

10.4

fMAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

181

168

154

134

MHz

Input Module Propagation Delays

tINYH

Pad-to-Y HIGH

0.7

0.8

0.9

1.1

1.5

tINYL

Pad-to-Y LOW

0.6

0.7

0.8

1.0

1.3

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check

the hold time for this macro.

4. Delays based on 35pF loading.

A40MX02 Datasheet(PDF) 44 Page - Microsemi Corporation

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