A40MX02 datasheet(68/142 Pages) MICROSEMI

68 / 142 page

40MX and 42MX FPGA Families

1- 64

R e v i sio n 1 1

Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays1

tPD1

Single Module

1.9

2.1

2.4

2.8

4.0

tCO

Sequential Clock-to-Q

2.0

2.2

2.5

3.0

4.2

tGO

Latch G-to-Q

1.9

2.1

2.4

2.8

4.0

tRS

Flip-Flop (Latch) Reset-to-Q

2.2

2.4

2.8

3.3

4.6

Logic Module Predicted Routing Delays2

tRD1

FO = 1 Routing Delay

1.1

1.2

1.4

1.6

2.3

tRD2

FO = 2 Routing Delay

1.5

1.6

1.8

2.1

3.0

tRD3

FO = 3 Routing Delay

1.8

2.0

2.3

2.7

3.8

tRD4

FO = 4 Routing Delay

2.2

2.4

2.7

3.2

4.5

tRD8

FO = 8 Routing Delay

3.6

4.0

4.5

5.3

7.5

Logic Module Sequential Timing3, 4

tSUD

Flip-Flop (Latch)

Data Input Set-Up

0.5

0.6

0.7

0.9

tHD

Flip-Flop (Latch) Data Input Hold

0.0

tSUENA

Flip-Flop (Latch) Enable Set-Up

1.0

1.1

1.2

1.4

2.0

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch)

Clock Active Pulse Width

4.8

5.3

6.0

7.1

9.9

tWASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

6.2

6.9

7.9

9.2

12.9

Flip-Flop Clock Input Period

9.5

10.6

12.0

14.1

19.8

tINH

Input Buffer Latch Hold

0.0

tINSU

Input Buffer Latch Set-Up

0.7

0.8

0.9

1.01

1.4

tOUTH

Output Buffer Latch Hold

0.0

tOUTSU

Output Buffer Latch Set-Up

0.7

0.8

0.89

1.01

1.4

fMAX

Flip-Flop (Latch) Clock Frequency

129

117

108

MHz

Notes:

1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external

PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 68 Page - Microsemi Corporation

A40MX02 Datasheet(HTML) 68 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL