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A40MX02 Datasheet(PDF) 77 Page - Microsemi Corporation |
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A40MX02 Datasheet(HTML) 77 Page - Microsemi Corporation |
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77 / 142 page  40MX and 42MX FPGA Families Re vi s i on 11 1 - 73 TTL Output Module Timing5 (continued) tLH I/O Latch Output Hold 0.0 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O 7.7 8.5 9.6 11.3 15.9 ns tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O 14.8 16.5 18.7 22.0 30.8 ns dTLH Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF dTHL Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF CMOS Output Module Timing5 tDLH Data-to-Pad HIGH 4.8 5.3 5.5 6.4 9.0 ns tDHL Data-to-Pad LOW 3.5 3.9 4.1 4.9 6.8 ns tENZH Enable Pad Z to HIGH 3.6 4.0 4.5 5.3 7.4 ns tENZL Enable Pad Z to LOW 3.4 4.0 5.0 5.8 8.2 ns tENHZ Enable Pad HIGH to Z 7.2 8.0 9.0 10.7 14.9 ns tENLZ Enable Pad LOW to Z 6.7 7.5 8.5 9.9 13.9 ns tGLH G-to-Pad HIGH 6.8 7.6 8.6 10.1 14.2 ns tGHL G-to-Pad LOW 6.8 7.6 8.6 10.1 14.2 ns tLSU I/O Latch Set-Up 0.7 0.7 0.8 1.0 1.4 ns tLH I/O Latch Hold 0.0 0.0 0.0 0.0 0.0 ns tLCO I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O 7.7 8.5 9.6 11.3 15.9 ns tACO Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O 14.8 16.5 18.7 22.0 30.8 ns dTLH Capacitive Loading, LOW to HIGH 0.05 0.05 0.06 0.07 0.10 ns/pF dTHL Capacitive Loading, HIGH to LOW 0.04 0.04 0.05 0.06 0.08 ns/pF tHEXT Input Latch External Hold FO = 32 FO = 486 3.9 4.6 4.3 5.2 4.9 5.8 5.7 6.9 8.1 9.6 ns ns tP Minimum Period (1/fMAX) FO = 32 FO = 486 7.8 8.6 8.7 9.5 9.5 10.4 10.8 11.9 18.2 19.9 ns ns Table 1-37 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (continued) (Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) –3 Speed –2 Speed –1 Speed Std Speed –F Speed Units Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. |
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