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A40MX02 Datasheet(PDF) 10 Page - Microsemi Corporation |
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A40MX02 Datasheet(HTML) 10 Page - Microsemi Corporation |
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10 / 142 page  40MX and 42MX FPGA Families 1- 6 R ev isio n 1 1 pins or from the internal array and can be used as a secondary register clock, register clear, or output enable. Figure 1-7 • Clock Networks of 42MX Devices Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals. Figure 1-8 • Quadrant Clock Network of A42MX36 Devices CLKB CLKA From Pads Clock Drivers CLKMOD CLKINB CLKINA S0 S1 Internal Signal CLKO(17) CLKO(16) CLKO(15) CLKO(2) CLKO(1) Clock Tracks Quad Clock Modul QCLKA QCLKB *QCLK1IN S0 S1 QCLK1 Quad Clock Modul *QCLK2IN S0 S1 QCLK2 Quad Clock Modul QCLKC QCLKD *QCLK3IN S0 S1 QCLK3 Quad Clock Modul *QCLK4IN S0 S1 QCLK4 |
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