A40MX02 datasheet(71/142 Pages) MICROSEMI

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40MX and 42MX FPGA Families

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Table 1-36 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Combinatorial Functions1

tPD

Internal Array Module Delay

1.2

1.3

1.5

1.8

2.5

tPDD

Internal Decode Module Delay

1.4

1.6

1.8

2.1

3.0

Logic Module Predicted Routing Delays2

tRD1

FO = 1 Routing Delay

0.8

0.9

1.0

1.2

1.7

tRD2

FO = 2 Routing Delay

1.0

1.2

1.3

1.5

2.1

tRD3

FO = 3 Routing Delay

1.3

1.4

1.6

1.9

2.6

tRD4

FO = 4 Routing Delay

1.5

1.7

1.9

2.2

3.1

tRD5

FO = 8 Routing Delay

2.4

2.7

3.0

3.6

5.0

Logic Module Sequential Timing3, 4

tCO

Flip-Flop Clock-to-Output

1.3

1.4

1.6

1.9

2.7

tGO

Latch Gate-to-Output

1.2

1.3

1.5

1.8

2.5

tSUD

Flip-Flop (Latch) Set-Up Time

0.3

0.4

0.5

0.7

tHD

Flip-Flop (Latch) Hold Time

0.0

tRO

Flip-Flop (Latch) Reset-to-Output

1.4

1.6

1.8

2.1

2.9

tSUENA

Flip-Flop (Latch) Enable Set-Up

0.4

0.5

0.6

0.8

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch)

Clock Active Pulse Width

3.3

3.7

4.2

4.9

6.9

tWASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.4

4.8

5.3

6.5

9.0

Input Module Propagation Delays

tINPY

Input Data Pad-to-Y

1.0

1.1

1.3

1.5

2.1

tINGO

Input Latch Gate-to-Output

1.3

1.4

1.6

1.9

2.6

tINH

Input Latch Hold

0.0

tINSU

Input Latch Set-Up

0.5

0.6

0.7

1.0

tILA

Latch Active Pulse Width

4.7

5.2

5.9

6.9

9.7

Notes:

1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.

External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an

external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 71 Page - Microsemi Corporation

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