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A40MX02 Datasheet(PDF) 69 Page - Microsemi Corporation |
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A40MX02 Datasheet(HTML) 69 Page - Microsemi Corporation |
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69 / 142 page  40MX and 42MX FPGA Families Re vi s i on 11 1 - 65 Input Module Propagation Delays tINYH Pad-to-Y HIGH 1.5 1.6 1.9 2.2 3.1 ns tINYL Pad-to-Y LOW 1.1 1.3 1.4 1.7 2.4 ns tINGH G to Y HIGH 2.0 2.2 2.5 2.9 4.1 ns tINGL G to Y LOW 2.0 2.2 2.5 2.9 4.1 ns Input Module Predicted Routing Delays2 tIRD1 FO = 1 Routing Delay 2.6 2.9 3.2 3.8 5.3 ns tIRD2 FO = 2 Routing Delay 2.9 3.2 3.7 4.3 6.1 ns tIRD3 FO = 3 Routing Delay 3.3 3.6 4.1 4.9 6.8 ns tIRD4 FO = 4 Routing Delay 3.6 4.0 4.6 5.4 7.6 ns tIRD8 FO = 8 Routing Delay 5.1 5.6 6.4 7.5 10.5 ns Global Clock Network tCKH Input LOW to HIGH FO = 32 FO = 384 4.4 4.8 4.8 5.3 5.5 6.0 6.5 7.1 9.0 9.9 ns ns tCKL Input HIGH to LOW FO = 32 FO = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 384 5.7 6.6 6.3 7.4 7.1 8.3 8.4 9.8 11.8 13.7 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 384 5.3 6.2 5.9 6.9 6.7 7.9 7.8 9.2 11.0 12.9 ns ns tCKSW Maximum Skew FO = 32 FO = 384 0.5 2.2 0.5 2.4 0.6 2.7 0.7 3.2 1.0 4.5 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 384 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 384 3.9 4.5 4.3 4.9 4.9 5.6 5.7 6.6 8.0 9.2 ns ns tP Minimum Period FO = 32 FO = 384 7.0 7.7 7.8 8.6 8.4 9.3 9.7 10.7 16.2 17.8 ns ns fMAX Maximum Frequency FO = 32 FO = 384 142 129 129 117 119 108 103 94 62 56 MHz MHz Table 1-35 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (continued) (Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C) –3 Speed –2 Speed –1 Speed Std Speed –F Speed Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Notes: 1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. |
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