A40MX02 datasheet(64/142 Pages) MICROSEMI

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40MX and 42MX FPGA Families

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Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Units

Parameter / Description

Min. Max. Min. Max.

Min. Max. Min. Max. Min. Max.

Logic Module Propagation Delays1

tPD1

Single Module

1.4

1.5

1.7

2.0

2.8

tCO

Sequential Clock-to-Q

1.4

1.6

1.8

2.1

3.0

tGO

Latch G-to-Q

1.4

1.5

1.7

2.0

2.8

tRS

Flip-Flop (Latch) Reset-to-Q

1.6

1.7

2.0

2.3

3.3

Logic Module Predicted Routing Delays2

tRD1

FO = 1 Routing Delay

0.8

0.9

1.0

1.2

1.6

tRD2

FO = 2 Routing Delay

1.0

1.2

1.3

1.5

2.1

tRD3

FO = 3 Routing Delay

1.3

1.4

1.6

1.9

2.7

tRD4

FO = 4 Routing Delay

1.6

1.7

2.0

2.3

3.2

tRD8

FO = 8 Routing Delay

2.6

2.9

3.2

3.8

5.3

Logic Module Sequential Timing3,4

tSUD

Flip-Flop (Latch)

Data Input Set-Up

0.3

0.4

0.5

0.7

tHD

Flip-Flop (Latch) Data Input Hold

0.0

tSUENA

Flip-Flop (Latch) Enable Set-Up

0.7

0.8

0.9

1.0

1.4

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch)

Clock Active Pulse Width

3.4

3.8

4.3

5.0

7.1

tWASYN

Flip-Flop (Latch)

Asynchronous Pulse Width

4.5

5.0

5.6

6.6

9.2

Flip-Flop Clock Input Period

6.8

7.6

8.6

10.1

14.1

tINH

Input Buffer Latch Hold

0.0

tINSU

Input Buffer Latch Set-Up

0.5

0.6

0.7

1.0

tOUTH

Output Buffer Latch Hold

0.0

tOUTSU

Output Buffer Latch Set-Up

0.5

0.6

0.7

1.0

fMAX

Flip-Flop (Latch) Clock Frequency

215

195

179

156

MHz

Notes:

1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is

appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external

PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 64 Page - Microsemi Corporation

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