A40MX02 datasheet(87/142 Pages) MICROSEMI

87 / 142 page

40MX and 42MX FPGA Families

Re vi s i on 11

1 - 83

Pin Descriptions

CLK/A/B, I/O

Global Clock

Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX

devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an

I/O.

DCLK, I/O

Diagnostic Clock

Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

GND

Ground

Input LOW supply voltage.

I/O

Input/Output

Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and

CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.

In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all

dual-purpose pins when configured as I/Os as well.

Low Power Mode

Controls the low power mode of all 42MX devices. The device is placed in the low power mode by

connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned

OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.

The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume

normal operation in 200 µs after the LP pin is driven to a logic LOW.

MODE

Mode

Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to

provide verification capability. The MODE pin should be terminated to GND through a 10k

Ω resistor so

that the MODE pin can be pulled HIGH when required.

No Connection

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

PRA, I/O

PRB, I/O

Probe A/B

The Probe pin is used to output data from any user-defined design node within the device. Each

diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of

any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has

been completed. The pin's probe capabilities can be permanently disabled to protect programmed design

confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O

when the MODE pin is LOW.

QCLKA/B/C/D, I/O

Quadrant Clock

Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can

function as user I/Os.

Table 1-40 • Configuration of Unused I/Os

Device

Configuration

A40MX02, A40MX04

Pulled LOW

A42MX09, A42MX16

Pulled LOW

A42MX24, A42MX36

Tristated

A40MX02 Datasheet(PDF) 87 Page - Microsemi Corporation

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