A40MX02 datasheet(86/142 Pages) MICROSEMI

86 / 142 page

40MX and 42MX FPGA Families

1- 82

R e v i sio n 1 1

TTL Output Module Timing5

tENLZ

Enable Pad LOW to Z

6.9

7.6

8.7

10.2

14.3

tGLH

G-to-Pad HIGH

4.9

5.5

6.2

7.3

10.2

tGHL

G-to-Pad LOW

4.9

5.5

6.2

7.3

10.2

tLSU

I/O Latch Output Set-Up

0.7

0.8

1.0

1.4

tLH

I/O Latch Output Hold

0.0

tLCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.9

8.8

10.0

11.8

16.5

tACO

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

10.9

12.1

13.7

16.1

22.5

dTLH

Capacitive Loading, LOW to HIGH

0.10

0.11

0.12

0.14

0.20 ns/pF

dTHL

Capacitive Loading, HIGH to LOW

0.10

0.11

0.12

0.14

0.20 ns/pF

CMOS Output Module Timing5

tDLH

Data-to-Pad HIGH

4.9

5.5

6.2

7.3

10.3

tDHL

Data-to-Pad LOW

3.4

3.8

4.3

5.1

7.1

tENZH

Enable Pad Z to HIGH

3.7

4.1

4.7

5.5

7.7

tENZL

Enable Pad Z to LOW

4.1

4.6

5.2

6.1

8.5

tENHZ

Enable Pad HIGH to Z

7.4

8.2

9.3

10.9

15.3

tENLZ

Enable Pad LOW to Z

6.9

7.6

8.7

10.2

14.3

tGLH

G-to-Pad HIGH

7.0

7.8

8.9

10.4

14.6

tGHL

G-to-Pad LOW

7.0

7.8

8.9

10.4

14.6

tLSU

I/O Latch Set-Up

0.7

0.8

1.0

1.4

tLH

I/O Latch Hold

0.0

tLCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.9

8.8

10.0

11.8

16.5

Table 1-39 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (continued)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Notes:

1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.

External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an

external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 86 Page - Microsemi Corporation

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