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A40MX02 Datasheet(PDF) 80 Page - Microsemi Corporation |
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A40MX02 Datasheet(HTML) 80 Page - Microsemi Corporation |
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80 / 142 page ![]() 40MX and 42MX FPGA Families 1- 76 R e v i sio n 1 1 Global Clock Network tCKH Input LOW to HIGH FO = 32 FO = 635 2.7 3.0 3.0 3.3 3.4 3.8 4.0 4.4 5.6 6.2 ns ns tCKL Input HIGH to LOW FO = 32 FO = 635 3.8 4.9 4.2 5.4 4.8 6.1 5.6 7.2 7.8 10.1 ns ns tPWH Minimum Pulse Width HIGH FO = 32 FO = 635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tPWL Minimum Pulse Width LOW FO = 32 FO = 635 1.8 2.0 2.0 2.2 2.2 2.5 2.6 2.9 3.6 4.1 ns ns tCKSW Maximum Skew FO = 32 FO = 635 0.8 0.8 0.8 0.8 0.9 0.9 1.0 1.0 1.4 1.4 ns ns tSUEXT Input Latch External Set-Up FO = 32 FO = 635 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns ns tHEXT Input Latch External Hold FO = 32 FO = 635 2.8 3.3 3.2 3.7 3.6 4.2 4.2 4.9 5.9 6.9 ns ns tP Minimum Period (1/fMAX) FO = 32 FO = 635 5.5 6.0 6.1 6.6 6.6 7.2 7.6 8.3 12.7 13.8 ns ns fMAX Maximum Datapath Frequency FO = 32 FO = 635 180 166 164 151 151 139 131 121 79 73 MHz MHz TTL Output Module Timing5 tDLH Data-to-Pad HIGH 2.6 2.8 3.2 3.8 5.3 ns tDHL Data-to-Pad LOW 3.0 3.3 3.7 4.4 6.2 ns tENZH Enable Pad Z to HIGH 2.7 3.0 3.3 3.9 5.5 ns tENZL Enable Pad Z to LOW 3.0 3.3 3.7 4.3 6.1 ns tENHZ Enable Pad HIGH to Z 5.3 5.8 6.6 7.8 10.9 ns Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation) (Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C) –3 Speed –2 Speed –1 Speed Std Speed –F Speed Parameter / Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the Timer utility. 4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 5. Delays based on 35 pF loading. |
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