AM79C976 datasheet(296/309 Pages) AMD

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APPENDIX B

-1

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APPENDIX B: MII MANAGEMENT REGISTERS

As specified in the IEEE standard, the basic register

set consists of the Control Register (Register 0) and

the Status Register (Register 1). The extended register

set consists of Registers 2 to 31 (decimal). All PHYs

that provide an MII shall incorporate the basic register

set. Both sets of registers are accessible through the

MII Management Interface.

Table 1 lists the most interesting registers.

Control Register (Register 0)

Table 2 shows the MII Management Control Register

(Register 0).

Table B-1. MII Management Register Set

Table B-2. MII Management Control Register (Register 0)

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Address

Basic/

Extended

0MII Control

MII Status

2-3

PHY Identifier

Auto-Negotiation

Auto-Negotiation Link

Partner Ability

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1RWH

Soft Reset

When write:

1 = PHY software reset

0 = normal operation

When read:

1 = reset in process

0 = reset done

R/W, SC

Loopback

1 = enables Loopback mode

0 = disables Loopback mode

R/W

Speed Selection

1 = 100 Mbps

0 = 10 Mbps

R/W

Auto-Negotiation Enable

1 = enable Auto-Negotiation

0 = disable Auto-Negotiation

R/W

Power Down

1 = power down, 0 = normal operation

R/W

Isolate

1 = electrically isolate PHY from MII

0 = normal operation

R/W

Restart Auto-Negotiation

1 = restart Auto-Negotiation

0 = normal operation

R/W, SC

Duplex Mode

1 = full duplex

0 = half duplex

R/W

Collision Test

1 = enable COL signal test

0 = disable COL signal test

R/W

6-0

Reserved

Write as 0, ignore on read

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