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Electronic Components Datasheet Search |
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Electronic Components Datasheet Search |
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AM79C976 Datasheet(PDF) 306 Page - Advanced Micro Devices |
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AM79C976 Datasheet(HTML) 306 Page - Advanced Micro Devices |
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306 / 309 page  INDEX-7 Am79C976 8/01/00 P R E L I M INARY PCI Latency Timer Register Offset 0Dh . . . . . . . . . . . . . . . . . . . . . . . . . .115 PCI MAX_LAT Register Offset 3Fh . . . . . . . . . . . . . . . . . . . . . . . . . .119 PCI Memory Mapped I/O Base Address Register Offset 14h . . . . . . . . . . . . . . . . . . .116 PCI MIN_GNT Register Offset 3Eh . . . . . .118 PCI Next Item Pointer Register Offset 45h . . . . . . . . . . . . . . . . . . . . . . . . . .119 PCI PMCSR Bridge Support Extensions Register Offset 4Ah . . . . . . . . . . . . . . . . . . .121 PCI Power Management Capabilities Register (PMC) Offset 46h . . . . . . . . . . . . .119 PCI Power Management Control/Status Register (PMCSR) Offset 48h . . . . . . . . . . .120 PCI Programming Interface Register Offset 09h . . . . . . . . . . . . . . . . . . . . . . . . . .114 PCI Revision ID Register Offset 08h . . . . . . . . . . . . . . . . . . . . . . . . . .114 PCI Status Register Offset 06h . . . . . . . . . .113 PCI Sub-Class Register Offset 0Ah . . . . . .114 PCI Subsystem ID Register Offset 2Eh . . . . . . . . . . . . . . . . . . . . . . . . . .117 PCI Subsystem Vendor ID Register Offset 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . .116 PCI Vendor ID Register . . . . . . . . . . . . . . .111 PCI Vendor ID Register Offset 00h . . . . . .111 PCIDATA0 PCI DATA Register Zero Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .161 PCIDATA1 PCI DATA Register One Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .161 PCIDATA2 PCI DATA Register Two Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .162 PCIDATA3 PCI DATA Register Three Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .162 PCIDATA4 PCI DATA Register Four Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .162 PCIDATA5 PCI DATA Register Five Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .162 PCIDATA6 PCI DATA Register Six Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . .162 PCIDATA7 PCI DATA Register Seven Alias Register . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Peripheral Component Interconnect (PCI) bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PHY Access Register . . . . . . . . . . . . . . . . . 163 PHY Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PHY_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Physical Dimensions . . . . . . . . . . . . . . . . . . 285 Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 267 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 24 Pin Designations by Group . . . . . . . . . . . . . . 21 Pin Designations by Pin Number (PQR208) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PMAT0 OnNow Pattern Register 0 . . . . . . . . . . . . 164 PMAT1 OnNow Pattern Register1 . . . . . . . . . . . . 164 PMC_A PCI Power Management Capabilities Alias Register . . . . . . . . . . . . . . . . . . . . . . 165 PME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power Management Event . . . . . . . . . . . . . . . 26 Power Management Interface . . . . . . . . . . . . 22 Power Management Support . . . . . . . . . . . . . 99 Power on Reset . . . . . . . . . . . . . . . . . . . . . . 105 Power Savings Mode . . . . . . . . . . . . . . . . . . . 99 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . 23 Power Supply Current . . . . . . . . . . . . . . . . . 268 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . 31 PQR208 Plastic Quad Flat Pack (measured in millimeters) . . . . . . . . . . . . . . 285 Preemption During Burst Transaction . . . 48, 50 Preemption During Non-Burst Transaction . . . . . . . . . . . . . . . . . . . . . . .48, 49 Programmable Inter Packet Gap (IPG) . . . . . . 2 Programmable Registers . . . . . . . . . . . . . . . 262 R RAP Register Address Port . . . . . . . . . . . . . . . 172 RAP Register . . . . . . . . . . . . . . . . . . . . . . . . 172 RCV_RING_LEN Receive Ring Length Register . . . . . . . . . 165 RDRA and TDRA . . . . . . . . . . . . . . . . . . . . 226 Receive Address Match . . . . . . . . . . . . . . . . . 72 |
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