AM79C976 datasheet(102/309 Pages) AMD

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102

Am79C976

8/01/00

P R E L I M INARY

ternal pointers to the current descriptors will be lost,

and the Am79C976 controller will not start where it left

off.

If Magic Packet mode is disabled by the assertion of

PG, then in order to immediately re-enable Magic

Packet mode, the PG pin must remain asserted for at

least 200 ns before it is deasserted. If Magic Packet

mode is disabled by clearing the register bits, then it

may be immediately re-enabled by setting MPEN_EE

or MPEN_SW back to 1.

The PCI bus interface clock (CLK) is not required to be

running while the device is operating in Magic Packet

mode. Either of the INTA, the LED pins, RWU, or the

PME signal may be used to indicate the receipt of a

Magic Packet frame when the CLK is stopped.

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In the OnNow Pattern Match Mode, the Am79C976

controller compares the incoming packets with up to

eight patterns stored in the Pattern Match RAM (PMR).

The stored patterns can be compared with part or all of

incoming packets, depending on the pattern length and

the way the PMR is programmed. When a pattern

match has been detected, then PMAT_DET bit (STAT0,

bit 12) is set. This causes the PME_STATUS bit

(PMCSR, bit 15) to be set, which in turn will assert the

PME pin if the PME_EN bit (PMCSR, bit 8) is set.

Patter n Match m ode is enabled by setting th e

PMAT_MODE bit (CMD7,bit 3).The RUN bit (CMD0, bit

0) and RX.SUSPEND bit (CMD0, bit 3) must also be

set. If using the legacy registers, STRT (CSR0, bit 1)

and SPND (CSR5, bit 0) must be set. Because Pattern

Match mode must be configured by software, it is not

possible to enable Pattern Match mode directly from

the EEPROM.

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The PMR is organized as an array of 64 words by 40

bits as shown in Figure 45. The PMR is programmed

indirectly through the PMAT0 and PMAT1 registers. For

compatibility with legacy controllers, the PMR may also

be programmed through BCR45, BCR46, and BCR47.

Pattern Match mode must be disabled (PMAT_MODE

bit cleared) to allow reading or writing the PMR.

A write access to the PMR begins with a write to the

PMAT0 register. Bits 6:0 of PMAT0 specify the address

in the PMR and bits 31:8 contain the data to be written

to bits 23:0 of the specified address in the PMR. This is

followed by a write to the PMAT1 register, with bits 15:0

of PMAT1 containing the data to be written to bits 39:24

of the specified address in the PMR. The actual write to

the PMR occurs when PMAT1 is written.

A read access to the PMR also begins with a write to

the PMAT0 register. Bits 6:0 of PMAT0 specify the ad-

dress in the PMR to be read and the remaining bits of

PMAT0 are ignored. This write is followed by a read of

PMAT0, which returns bits 23:0 of PMR in bit positions

31:8 and a read of PMAT1, which returns bits 39:24 of

PMR in bit positions 15:0. These reads may be done in

any order.

The first two 40-bit words in the PMR serve as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. Byte 0 of the first word contains the Pattern Enable

bits. Any bit position set in this byte enables the corre-

sponding match pattern in the PMR. As an example, if

bit 3 is set, then Pattern 3 is enabled for matching.

Bytes 1 to 4 in the first word are pointers to the begin-

ning of the patterns 0 to 3, and bytes 1 to 4 in the sec-

ond word are pointers to the beginning of the patterns

4 to 7, respectively. Byte 0 of the second word has no

function associated with it. Byte 0 of words 2 to 63 is

the Control Field of the PMR. Bit 7 of this field is the

End of Pattern (EOP) bit. When this bit is set, it indi-

cates the end of a pattern in the PMR.

Bits 6-4 of the Control Field byte are the SKIP bits. The

value of the SKIP field indicates the number of the

Dwords to be skipped before the pattern in this PMR

word is compared with data from the incoming frame. A

maximum of seven Dwords may be skipped. Bits 3-0 of

the Control Field byte are the MASK bits. These bits

correspond to the pattern match bytes 3-0 of the same

PMR word (PMR bytes 4-1). If bit n of this field is 0, then

byte n of the corresponding pattern word is ignored. If

this field is programmed to 3, then bytes 0 and 1 of the

pattern match field (bytes 2 and 1 of the word) are used

and bytes 3 and 2 are ignored in the pattern matching

operation.

The contents of the PMR are not affected by any reset.

The contents are undefined after a power-up reset

(POR).

AM79C976 Datasheet(PDF) 102 Page - Advanced Micro Devices

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