AM79C976 datasheet(104/309 Pages) AMD

104 / 309 page

104

Am79C976

8/01/00

P R E L I M INARY

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to con-

trol the data flow in the Data registers according to the

current instruction.

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Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial

Shift Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the BSR

cell shown in Table 18.

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Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 19).

Note: The content of the Device ID register is the

same as the content of CSR88.

Reset

There are five different types of RESET operations that

may be p e r fo r med on th e A m 79 C976 dev ic e,

H_RESET, EE_RESET, S_RESET, STOP, and POR.

The following is a description of each type of RESET

operation.

+B5(6(7

Hardware Reset (H_RESET) is an Am79C976 reset

operation that has been created by the proper asser-

tion of the RST pin of the Am79C976 device while the

PG pin is HIGH. When the minimum pulse width timing

as specified in the RST pin description has been satis-

fied, then an internal reset operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to their default value. Note that there are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will reset the internal

state machines. Following the end of the H_RESET op-

eration, the Am79C976 controller will attempt to read

the EEPROM device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the

Am79C976 controller will be in 16-bit I/O mode after

the reset operation. A DWord write operation to the

RDP (I/O offset 10h) must be performed to set the

device into 32-bit I/O mode.

((B5(6(7

Prior to starting a read of the serial EEPROM, the

Am79C976 controller resets all the registers that can

be programmed from the EEPROM. This provides a

consistent starting point for register programming.

EE_RESET is also generated following EEPROM read

if the EEPROM CRC check fails.

Table 17. IEEE 1149.1 Supported Instruction

Summary

Instruction

Name

Instruc-

tion

Code

Description

Mode

Selected

Data

EXTEST

0000

External

Test

BSR

IDCODE

0001

ID Code

Inspection

Normal

ID REG

SAMPLE

0010

Sample

Boundary

Normal

BSR

TRIBYP

0011

Force Float

Normal

Bypass

SETBYP

0100

Control

Boundary To

1/0

Test

Bypass

BYPASS

1111

Bypass

Scan

Normal

Bypass

Table 18. BSR Mode Of Operation

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Table 19. Device ID Register

Bits 31-28

Version

Bits 27-12

Part Number:

0010 0110 0010 1000b

(2628h)

Bits 11-1

Manufacturer ID. The 11 bit manufacturer ID

code for AMD is 00000000001 in accordance

with JEDEC publication 106-A.

Bit 0

Always a logic 1

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