AM79C976 datasheet(139/309 Pages) AMD

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8/01/00

Am79C976

139

P R E L I M INARY

CTRL0: Control0 Register

Offset 068h

This register contains several miscellaneous control

bits. Each byte of this register controls a single func-

tion. It is not necessary to do a read-modify-write oper-

ation to change a function’s settings if only a single byte

of the register is written.

All bits in this register are set to their default values by

H_RESET. All bits are also set to their default values

before EEPROM data are loaded or after an EEPROM

read failure.

The default value for all bits except for bits 11:8

(ROMTMG) is 0. The default value for the ROMTMG

field is 1001b.

Table 46. CTRL0: Control0 Register

Bit

Name

Description

31-25

RES

Reserved locations. Written as zeros and read as undefined.

BSWP

Byte Swap. This bit is used to choose between big and little Endian modes of operation. When

BSWP is set to a 1, big Endian mode is selected. When BSWP is set to 0, little Endian mode is

selected.

When big Endian mode is selected, the Am79C976 controller will swap the order of bytes on the

AD bus during a data phase on accesses to the FIFOs only. Specifically, AD[31:24] becomes Byte

0, AD[23:16] becomes Byte 1, AD[15:8] becomes Byte 2, and AD[7:0] becomes Byte 3 when big

Endian mode is selected. When little Endian mode is selected, the order of bytes on the AD bus

during a data phase is: AD[31:24] is Byte 3, AD[23:16] is Byte 2, AD[15:8] is Byte 1, and AD[7:0]

is Byte 0.

Byte swap only affects data transfers that involve the FIFOs. Initialization block transfers are not

affected by the setting of the BSWP bit. Descriptor transfers are not affected by the setting of the

BSWP bit. RDP, RAP, BDP and PCI configuration space accesses are not affected by the setting

of the BSWP bit. Address PROM transfers are not affected by the setting of the BSWP bit.

Expansion ROM accesses are not affected by the setting of the BSWP bit.

Note that the byte ordering of the PCI bus is defined to be little Endian. BSWP should not be set

to 1 when the Am79C976 controller is used in a PCI bus application.

This bit is an alias of CSR3, bit 2.

23:18

RES

Reserved locations. Written as zeros and read as undefined.

17-16

SRAM_TYPE

SSRAM Type. This field must be set up to indicate the type of external SSRAM that is connected

to the external memory interface.

15-12

RES

Reserved locations. Written as zeros and read as undefined.

SRAM_TYPE[1:0]

External Memory Type

Reserved

ZBT

Reserved

Pipelined Burst

AM79C976 Datasheet(PDF) 139 Page - Advanced Micro Devices

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