LM3421 datasheet(23/65 Pages) TI1

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TMR

11.5

FLT

1.24

RSNS

10V

10 k:

LM3421/23

DDRV

VCC

100 pF

100

DPOL

LM3421, LM3421-Q1

LM3423, LM3423-Q1

www.ti.com

SNVS574D – JULY 2008 – REVISED SEPTEMBER 2011

Figure 32. Boost Level-Shifted PWM Circuit

LM3423 ONLY: DPOL, FLT, TIMR, and LRDY

The LM3423 has four additional pins: DPOL, FLT, TIMR, and LRDY. The DPOL pin is simply used to invert the

DDRV polarity . If DPOL is left open, then it is internally pulled high and the polarity is correct for driving a series

N-channel dimFET. If DPOL is pulled low then the polarity is correct for using a series P-channel dimFET in high-

side dimming applications. For a parallel P-channel dimFET, as used in the buck topology, leave DPOL open for

proper polarity.

Among the LM3423's other additional pins are TIMR and FLT which can be used in conjunction with an input

disconnect MosFET switch as shown in Figure 33 to protect the module from various fault conditions.

A fault is detected and an 11.5 µA (typical) current is sourced from the TIMR pin whenever any of the following

conditions exist:

1. LED current is above regulation by more than 30%.

2. OVLO has engaged.

3. Thermal shutdown has engaged.

An external capacitor (CTMR) from TIMR to AGND programs the fault filter time as follows:

(33)

When the voltage on the TIMR pin reaches 1.24V, the device is latched off and the N-channel MosFET open

drain FLT pin transitions to a high impedance state. The TIMR pin will be immediately pulled to ground (reset) if

the fault condition is removed at any point during the filter period. Otherwise, if the timer expires, the fault will

remain latched until one of three things occurs:

1. The EN pin is pulled low long enough for the VCC pin to drop below 4.1V (approximately 200 ms).

2. The TIMR pin is pulled to ground.

3. A complete power cycle occurs.

When using the EN and OVP pins in conjunction with the RPD pull-down pin, a race condition exists when

exiting the disabled (EN low) state. When disabled, the OVP pin is pulled up to the output voltage because the

RPD pull-down is disabled, and this will appear to be a real OVLO condition. The timer pin will immediately rise

and latch the controller to the fault state. To protect against this behavior, a minimum timer capacitor (CTMR =

220pF) should be used. If fault latching is not required, short the TMR pin to AGND which will disable the FLT

flag function.

The LM3423 also includes an LED Ready (LRDY) flag to notify the system that the LEDs are in proper

regulation. The N-channel MosFET open drain LRDY pin is pulled low whenever any of the following conditions

are met:

1. VCC UVLO has engaged.

2. LED current is below regulation by more than 20%.

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Product Folder Links: LM3421 LM3421-Q1 LM3423 LM3423-Q1

LM3421 Datasheet(PDF) 23 Page - Texas Instruments

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