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HMS81032TL Datasheet(PDF) 36 Page - Hynix Semiconductor |
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HMS81032TL Datasheet(HTML) 36 Page - Hynix Semiconductor |
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36 / 77 page ![]() HMS81004E/08E/16E/24E/32E JUNE 2001 Ver 1.00 33 10. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. Prescaler consist of 12-bit binary counter. The clock sup- plied from oscillation circuit is input to prescaler(fex) The divided output from each bit of prescaler is provided to periphera hardwarel Clock to peripheral hardware can be stopped by bit4 (EN- PCK) of CKCTLR Register. ENPCK is set to “1” in reset state. Clock Control Register (W) CKCTLR ADDRESS : 0C7H INITIAL VALUE : --110111b 0 1 2 3 4 5 6 7 ENPCK 0: Stopped 1: Provided Figure 10-1 Block diagram of Clock Generator Internal system clock (CPU clock) PRESCALER ÷1 Peripheral clock ÷2 ÷4 ÷8 ÷16 ÷128 ÷256 ÷512 ÷1024 ÷32 ÷64 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 CLOCK PULSE fEX(MHz) PS0 PS3 PS2 PS4 PS1 PS10 PS9 PS5 PS6 PS7 4 Frequency period 4M 1M 500K 250K 2M 125K 62.5K 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906K 7.183K 15.63K 31.25K PS8 GENERATOR OSC CIRCUIT PS11 PS12 1.953K 512u 0.976K 1024u PS11 PS12 ÷2048 ÷4096 fex |
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