HMS81032TL datasheet(52/77 Pages) HYNIX

Part #	HMS81032TL

Description	HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

PDF	77 Pages

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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52 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.3 Interrupt accept mode

The interrupt priority order is determined by bit (IM1,

IM0) of IMOD register. The condition allow for accepting

interrupt is set state of the interrupt mask enable flag and

the interrupt enable bit must be “1”. In Reset state, these

IP3 - IP0 registers become all “0”.

Figure 14-2 Interrupt Enable & Request Flag

0: Disable

1: Enable

VALUE

R/W

INITIAL VALUE: 000- 000-B

ADDRESS: 0CEH

IENH

INT1E

MSB

LSB

T0E

T1E

INT2E

R/W

External interrupt 1

INITIAL VALUE: -00- ----B

ADDRESS: 0CCH

IENL

MSB

LSB

Timer1

R/W

Basic Interval Timer

Watchdog timer

External interrupt 2

Key scan

WDTE

R/W

BITE

KSCNE

T2E

Timer2

Timer0

R/W

INITIAL VALUE: 000- 000-B

ADDRESS: 0CFH

IRQH

INT1R

MSB

LSB

T0R

T1R

INT2R

R/W

External interrupt 1

INITIAL VALUE: -00- ----B

ADDRESS: 0CDH

IRQL

MSB

LSB

Timer1

R/W

Basic Interval Timer

Watchdog timer

External interrupt 2

Key scan

WDTR

R/W

BITR

KSCNR

T2R

Timer2

Timer0

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