HMS81032TL datasheet(53/77 Pages) HYNIX

53 / 77 page

HMS81004E/08E/16E/24E/32E

JUNE 2001 Ver 1.00

14.4 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the

interrupt latch is cleared to “0” by a reset or an instruction. Inter-

rupt acceptance sequence requires 8 fXIN after the completion of

the current instruction execution. The interrupt service task is ter-

minated upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

2. Interrupt request flag for the interrupt source accepted is

cleared to “0”.

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0

BTCL

7654

3210

IM 1

INITIAL VALUE: --00_0000B

ADDRESS: 0CAH

IMOD

IP1

IP0

R/W

IM 0

Interrupt mode register

Selection interrupt

00: Fixed by hardware

01: Changeable by IP3~IP0

Priority

R/W

0001: KSCNR

0010: INT1R

0011: INT2R

0101: T0R

0110: T1R

0111: T2R

1010: WDTR

1011: BITR

IP 2

IP 3

1x: Interrupt is inhibited

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